The next step of the TileFPGA testing is the SDRAM interface.
As you may see in the following video, writing to the SDRAM memory space seems successful, but reading back the data by refreshing the debugger view, shows that the memory is sparsely written (or ghost read).
This usually is an indicator of the clock phase, which can be addressed in the design’s clock generation phase. By adjusting the clock phase, the clock becomes in sync with the signals and hence the SDRAM is operating properly.
This concludes the TileFPGA testing for now. In the next blog the Hydro4 ADC interface will be checked.